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cy8c21345, cy8c21645 cy8c22345, cy8c 22345h, cy8c22645 automotive psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-55397 rev. *i revised march 18, 2011 features automotive electronics council (aec) q100 qualified powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? automotive a-grade: 3.0 v to 5.25 v operation at ?40 c to +85 c temperature range ? automotive e-grade: 4.75 v to 5.25 v operation at ?40 c to +125 c temperature range advanced peripherals (psoc ? blocks) ? six analog type ?e? psoc blocks provide: ? up to four comparators with digital-to-analog converters (dac) references ? up to 10-bit single or dual analog-to-digital converters (adcs) ? up to eight digital psoc blocks provide: ? 8 to 32-bit timers, counters , and pulse width modulators (pwms) ? one-shot, multi-shot mode in timers and pwms ? pwm with deadband in one digital block ? shift register, cyclical redundancy check (crc), and pseudo random sequence (prs) modules ? full- or half-duplex uarts ? spi masters or slaves, 8- to 16-bit variable data length ? connectable to all general-purpose i/o (gpio) pins ? complex peripherals by combining blocks ? powerful synchronization support, analog module operations can be synchronized by digital blocks or external signals. high-speed 10-bit successive a pproximation register (sar) adc with sample and hold optimized for embedded control cy8c22345h devices integrate immersion ? touchsense ? haptics technology for erm drive control precision, programmable clocking ? internal oscillator up to 24 mhz ? high accuracy 24 mhz with optional 32-khz crystal and phase locked loop (pll) ? optional external oscillator, up to 24 mhz ? internal low speed, low-power oscillator for watchdog and sleep functionality flexible on-chip memory ? up to 16 kb flash program st orage, 1000 erase/write cycles ? up to 1 kb sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash optimized capsense ? resource ? supports two capsense channels with simultaneous scanning ? two current dacs provide programmable sensor tuning in firmware ? two dedicated clock resources for capsense ? two dedicated 16-bit timers/counters for capsense scanning versatile analog mux ? common internal analog bus ? simultaneous connection of i/o combinations programmable pin configurations ? 25 ma sink, 10 ma drive on all gpios ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpios ? analog input on all gpios ? configurable interrupt on all gpios additional system resources: ? i 2 c master, slave, or multi-master ? operation up to 400 khz ? hardware address detection feature ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference ? hardware real time clock (rtc) block digital system sram 1kb/512b interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k/8k digital block array multiply accum. internal voltage ref. digital clocks por and lvd system resets system resources analog system analog ref analog input muxing i 2 c system bus analog block array port 2 port 1 port 0 capsense digital resources port 3 port 4 10-bit sar adc rtc block diagram [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 2 of 36 contents psoc functional overview .............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 haptics ts2000 controller .......................................... 4 additional system resources ..................................... 5 psoc device characteristics . ..................................... 5 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. ......................... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 28-pin part pinout ....................................................... 8 48-pin part pinout ....................................................... 9 registers ......................................................................... 11 register conventions ................................................ 11 register mapping tables .......................................... 11 electrical specifications ................................................ 14 absolute maximum ratings ... .................................... 15 operating temperature ............................................ 15 dc electrical characteristics ..................................... 16 ac electrical characteristics ..................................... 21 packaging information ................................................... 26 package dimensions ................................................. 26 thermal impedances ................................................ 27 capacitance on crystal pins ............................ ........ 27 solder reflow peak temperat ure ............................. 27 tape and reel information .... ............................ ........ 28 development tool selection .. ............................ ........... 30 software .................................................................... 30 development kits ...................................................... 30 evaluation tools ........................................................ 30 device programmers ............. .................................... 31 accessories (emulation and programming) .............. 31 ordering information ...................................................... 32 ordering code definitions . ....................................... 33 document conventions ................................................. 34 acronyms used ......................................................... 34 units of measure ....................................................... 34 numeric naming .................... .................................... 34 document history page ................................................. 35 sales, solutions, and legal information ...................... 36 worldwide sales and design s upport ......... .............. 36 products .................................................................... 36 psoc solutions ......................................................... 36 [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 3 of 36 psoc functional overview the psoc programmable system-on-chip series of products consists of many devices. these devices are designed to replace multiple traditional m cu-based system components with one low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, shown in the block diagram on page 1, consists of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows the combining of all the device resources into a complete custom system. the psoc family can have up to five i/o ports connecting to the global digital and analog interconnects, providing access to eight digital blocks [1] and six analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio. the m8c cpu core is a powerful processor with speeds up to 24 mhz (up to 12 mhz for e-grade devices), providing four mips (two mips for e-grade devices) 8-bit harvard architecture micro- processor. the cpu uses an interrupt controller to simplify the programming of real time embedded events. program execution is timed an d protected using the included sleep timer and watch dog timer (wdt). memory encompasses 16 kb of flash (8 kb for cy8c21x45 devices) for program storage, 1 kb of sram (512 bytes for cy8c21x45 devices) for data st orage, and eeprom emulation using the flash. program flash us es four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24-mhz internal main oscillator (imo). for a-grade devices the 24-mhz imo can also be doubled to 48 mhz for use by the digital system. a low-power 32-khz internal low-speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is required, t he 32.768 khz external crystal oscillator (eco) is available for use as a rtc, and can optionally generate a crystal-accurate 24 -mhz system clock using a pll. the clocks, together with progra mmable clock dividers (as a system resource), provide the flex ibility to integr ate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. each pin can also generate a system interrupt. digital system the digital system is composed of eight digital psoc blocks. each block is an 8-bit resource that may be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. figure 1. digital system block diagram [1] digital peripheral configurations are: pwms (8- to 32-bit) pwms with deadband (8- to 32-bit) counters (8- to 32-bit) timers (8- to 32-bit) one-shot and multi-shot modules full or half-duplex 8-bit uart with selectable parity (up to two full-duplex or four half-duplex) spi master and slave (up to four total) with programmable data length from 8 to 16 bits. shift register (1- to 32-bit) i 2 c master, slave, or multi-master (one available) crc/generator (16-bit) irda (up to two) prs generators (8- to 32-bit) note 1. cy8c22x45 devices have 2 digital rows with 8 digital blocks. cy8c21x45 devices only have 1 digital row with 4 digital blocks. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbc00 dbc01 dcc02 dcc03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0 port 4 port 3 dbc00 dbc01 dcc02 dcc03 row 1 row input configuration row output configuration [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 4 of 36 the digital blocks may be con nected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fami ly. this provides a choice of system resources for your applic ation. family resources are shown in table 1 on page 5. analog system the analog system of cy8c21x45 and cy8c22x45 psoc devices consists of a 10-bit sar adc and six configurable analog blocks. the programmable 10-bit sar adc is an optimized adc with a fast maximum sample rate. external filters are required on adc input channels for antialiasing. this ensures that any out-of-band content is not folded into the input signal band. reconfigurable analog resources allow creating complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (single or dual, with up to 10-bit resolution) pin-to-pin comparator single-ended comparators (up to four) with absolute (1.3 v) reference or dac reference precision voltage reference (1.3 v nominal) cy8c21x45 and cy8c22x45 devices have six limited-function- ality type 'e' analog blocks. t hese analog blocks are arranged in four columns. each column contains one continuous time (ct) type e block. the first two columns also have a switched capacitor (sc) type e block. refer to the psoc technical reference manual for cy8c21x45 and cy8c22x45 devices for detailed information on the type e analog blocks. figure 2. analog system block diagram haptics ts2000 controller the cy8c22x45h family of devi ces features an easy-to-use haptics controller resource with up to 14 different effects. these effects are available for use with three different, selectable erm modules. ace01 block array array input configuration aci1[1:0] aci0[1:0] reference generators bandgap agnd ase10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference 10 bit sar adc aci2[3:0] p0[0:7] ace00 ase11 aci1[1:0] aci1[1:0] amuxr amuxl ace11 ace10 [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 5 of 36 additional system resources system resources, some of which are listed in the previous sections, provide additional capability useful for complete systems. additional resources include a mac, low voltage detection, and power on rese t. the merits of each system resource are: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. additional digital resources and clocks dedicated to and optimized for capsense. rtc hardware block. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. the i 2 c module provides 0 to 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power on reset (por) circuit elimin ates the need for a system supervisor. an internal voltage reference provides an absolute reference for the analog system, including adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have varying numbers of digital and analog blocks. the following table lists the resources available for specific psoc device groups. th e psoc families covered by this datasheet are highlighted in the table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [2] up to 64 4 16 up to 12 4 4 12 2 kb 32 kb cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 16 1 kb 16 kb cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 bytes 16 kb cy8c24x94 [2] up to 56 1 4 up to 48 2 2 6 1 kb 16 kb cy8c24x23a [2] up to 24 1 4 up to 12 2 2 6 256 bytes 4 kb cy8c23x33 up to 25 1 4 up to 12 2 2 4 256 bytes 8 kb cy8c22x45 [2] up to 38 2 8 up to 38 0 4 6 [3] 1 kb 16 kb cy8c21x45 [2] up to 38 1 4 up to 38 0 4 6 [3] 512 bytes 8 kb cy8c21x34 [2] up to 28 1 4 up to 28 024 [3] 512 bytes 8 kb cy8c21x23 up to 16 1 4 up to 8 024 [3] 256 bytes 4 kb cy8c20x34 [2] up to 28 0 0 up to 28 003 [3, 4] 512 bytes 8 kb notes 2. automotive qualified devices available in this group. 3. limited analog functionality . 4. two analog blocks and one capsense ? block. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 6 of 36 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system des ign and time to market. develop your applications using a library of pr echaracterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated applicati on programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug envir onment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universa l asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this pr epopulates your project with apis and libraries that you can us e to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change c onfigurations at run time. in essence, this allows you to us e more than 100 percent of psoc's resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 7 of 36 c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug env ironment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context- sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation. designing with psoc designer the development process for the psoc? device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that a llow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functi ons to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applic ations in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. 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cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 8 of 36 pinouts the automotive cy8c21x45 and cy8c22x45 psoc devices are availabl e in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capa ble of digital i/o and connection to the common analog mux bus . however, v ss , v dd , and xres are not capable of digital i/o. 28-pin part pinout table 2. 28-pin part pinout (ssop) pin no. type pin name description digital analog figure 3. cy8c21345, cy8c22345, and cy8c22345h 28-pin psoc device 1 i/o i, mr p0[7] analog column mux input, c mod capacitor pin 2 i/o i, ml p0[5] analog column mux input, c mod capacitor pin 3 i/o i, ml p0[3] analog column mux input 4 i/o i, ml p0[1] analog column mux input 5 i/o i, ml p2[7] direct input to analog block 6 i/o ml p2[5] optional sar adc external reference (extref) 7 i/o ml p2[3] 8 i/o ml p2[1] 9 power v ss ground connection 10 i/o ml p1[7] i 2 c serial clock (scl) 11 i/o ml p1[5] i 2 c serial data (sda) 12 i/o ml p1[3] 13 i/o ml p1[1] crystal input (xtalin), i 2 c scl, issp-sclk [5] 14 power v ss ground connection 15 i/o mr p1[0] crystal output (xtalout), i 2 c sda, issp-sdata [5] 16 i/o mr p1[2] 17 i/o mr p1[4] optional external clock input (extclk) 18 i/o mr p1[6] 19 input xres active high external reset with internal pull-down 20 i/o mr p2[0] 21 i/o mr p2[2] 22 i/o mr p2[4] 23 i/o i, mr p2[6] direct input to analog block 24 i/o i, mr p0[0] analog column mux input 25 i/o i, mr p0[2] analog column mux input 26 i/o i, mr p0[4] analog column mux input 27 i/o i, mr p0[6] analog column mux input 28 power v dd supply voltage legend : a = analog, i = input, o = output, mr= right analog mux bus input, ml= left analog mux bus input. ssop 1 ai, mr, p0[7] ai, ml, p0[5] ai, ml, p0[3] ai, ml, p0[1] ai, ml, p2[7] extref, ml, p2[5] ml, p2[3] ml, p2[1] v ss i2c scl, ml, p1[7] i2c sda, ml, p1[5] ml, p1[3] xtalin, i2c scl, ml, p1[1] v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v dd p0[6], mr, ai p0[4], mr, ai p0[2], mr, ai p0[0], mr, ai p2[6], mr, ai p2[4], mr p2[2], mr p2[0], mr xres p1[6], mr p1[4], mr, extclk p1[2], mr p1[0], mr, i2c sda, xtalout note 5. these are the issp pins, which are not high z after exiting a reset state. see the psoc technical reference manual for cy8c21x45 and cy8c22x45 devices for details. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 9 of 36 48-pin part pinout note 6. these are the issp pins, which are not high z after exiting a reset state. see the psoc technical reference manual for cy8c21x45 and cy8c22x45 devices for details. table 3. 48-pin part pinout (ssop) pin no. type pin name description digital analog 1 i/o i, mr p0[7] analog column mux input, c mod capacitor pin figure 4. cy8c21645 and cy8c22645 48-pin psoc device 2 i/o i, ml p0[5] analog column mux input, c mod capacitor pin 3 i/o i, ml p0[3] analog column mux input 4 i/o i, ml p0[1] analog column mux input 5 i/o i, ml p2[7] direct input to analog block 6 i/o ml p2[5] optional sar adc external reference 7 i/o ml p2[3] 8 i/o ml p2[1] 9 power v dd supply voltage 10 i/o ml p4[5] 11 i/o ml p4[3] 12 i/o ml p4[1] 13 power v ss ground connection 14 i/o ml p3[7] 15 i/o ml p3[5] 16 i/o ml p3[3] 17 i/o ml p3[1] 18 nc not connected 19 nc not connected 20 i/o ml p1[7] i 2 c serial clock 21 i/o ml p1[5] i 2 c serial data 22 i/o ml p1[3] 23 i/o ml p1[1] crystal input (xtalin), i 2 c scl, issp-sclk [6] 24 power v ss 25 i/o mr p1[0] crystal output (xtalout), i 2 c sda, issp-sdata [6] 26 i/o mr p1[2] 27 i/o mr p1[4] optional external clock input 28 i/o mr p1[6] 29 nc not connected 30 nc not connected 31 i/o mr p3[0] 32 i/o mr p3[2] 33 i/o mr p3[4] 34 i/o mr p3[6] 35 input xres active high external reset with internal pull-down 36 i/o mr p4[0] 37 i/o mr p4[2] 38 i/o mr p4[4] 39 power v ss ground connection 40 i/o mr p2[0] ssop 1 ai, mr, p0[7] ai, ml, p0[5] ai, ml, p0[3] ai, ml, p0[1] ai, ml, p2[7] extref, ml, p2[5] ml, p2[3] ml, p2[1] nc i2c scl, ml, p1[7] i2c sda, ml, p1[5] ml, p1[3] xtalin, i2c scl, ml, p1[1] v ss 2 3 5 6 7 8 9 10 11 12 13 14 v dd p0[6], mr, ai p0[4], mr, ai p0[2], mr, ai p0[0], mr, ai p2[6], mr, ai p2[4], mr p2[2], mr p2[0], mr xres p1[6], mr p1[4], mr, extclk p1[2], mr p1[0], mr, i2c sda, xtalout ml, p4[5] ml, p4[3] ml, p4[1] ml, p3[7] ml, p3[5] ml, p3[3] ml, p3[1] nc v ss v dd nc nc p3[6], mr p3[4], mr p3[2], mr p3[0], mr p4[4], mr p4[2], mr p4[0], mr v ss 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 4 [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 10 of 36 41 i/o mr p2[2] 42 i/o mr p2[4] 43 i/o i, mr p2[6] direct input to analog block 44 i/o i, mr p0[0] analog column mux input 45 i/o i, mr p0[2] analog column mux input 46 i/o i, mr p0[4] analog column mux input 47 i/o i, mr p0[6] analog column mux input 48 power v dd supply voltage legend : a = analog, i = input, o = output, mr= right analog mux bus input, ml= left analog mux bus input table 3. 48-pin part pinout (ssop) (continued) pin no. type pin name description digital analog [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 11 of 36 registers this section lists the registers of this psoc device family by mapping tables. for detailed register information, refer to the psoc technical reference manual for cy8c21x45 and cy8c22x45 devices. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 4. abbreviations convention description rw read and write register or bit(s) r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 12 of 36 table 5. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 pwmvref0 c8 # prt2ie 09 rw 49 89 pwmvref1 c9 # prt2gs 0a rw 4a 8a idac_mode ca rw prt2dm2 0b rw 4b 8b pwm_src cb # prt3dr 0c rw 4c 8c ts_cr0 cc rw prt3ie 0d rw 4d 8d ts_cmph cd rw prt3gs 0e rw 4e 8e ts_cmpl ce rw prt3dm2 0f rw 4f 8f ts_cr1 cf rw prt4dr 10 rw csd0_dr0_l 50 r 90 cur pp d0 rw prt4ie 11 rw csd0_dr1_l 51 w 91 stk_pp d1 rw prt4gs 12 rw csd0_cnt_l 52 r 92 d2 prt4dm2 13 rw csd0_cr0 53 # 93 idx_pp d3 rw 14 csd0_dr0_h 54 r 94 mvr_pp d4 rw 15 csd0_dr1_h 55 w 95 mvw_pp d5 rw 16 csd0_cnt_h 56 r 96 i2c 0 _cfg d6 rw 17 csd0_cr1 57 rw 97 i2c 0 _scr d7 # 18 csd1_dr0_l 58 r 98 i2c 0 _dr d8 rw 19 csd1_dr1_l 59 w 99 i2c 0 _mscr d9 # 1a csd1_cnt_l 5a r 9a int_clr0 da rw 1b csd1_cr0 5b # 9b int_clr1 db rw 1c csd1_dr0_h 5c r 9c int_clr 2 dc rw 1d csd1_dr1_h 5d w 9d int_clr 3 dd rw 1e csd1_cnt_h 5e r 9e int_msk3 de rw 1f csd1_cr1 5f rw 9f int_msk 2 df rw dbc00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw a1 int_msk1 e1 rw dbc00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # a4 dbc01dr1 25 w asy_cr 65 # a5 dbc01dr2 26 rw cmp_cr1 66 rw a6 dec _cr0 e6 rw dbc01cr0 27 # 67 a7 dec_cr1 e7 rw dcc02dr0 28 # adc0_cr 68 # a8 mul 0 _x e8 w dcc02dr1 29 w adc1_cr 69 # a9 mul 0 _y e9 w dcc02dr2 2a rw sadc_dh 6a rw aa mul 0 _dh ea r dcc02cr0 2b # sadc_dl 6b rw ab mul 0 _dl eb r dcc03dr0 2c # tmp_dr0 6c rw ac acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw ad acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw ae acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw af acc0_dr2 ef rw dbc10dr0 30 # 70 rdi0ri b0 rw f0 dbc10dr1 31 w 71 rdi0syn b1 rw f1 dbc10dr2 32 rw ace00cr1 72 rw rdi0is b2 rw f2 dbc10cr0 33 # ace00cr2 73 rw rdi0lt0 b3 rw f3 dbc11dr0 34 # 74 rdi0lt1 b4 rw f4 dbc11dr1 35 w 75 rdi0ro0 b5 rw f5 dbc11dr2 36 rw ace01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr0 37 # ace01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12dr0 38 # 78 rdi1ri b8 rw f8 dcc12dr1 39 w 79 rdi1syn b9 rw f9 dcc12dr2 3a rw 7a rdi1is ba rw fa dcc12cr0 3b # 7b rdi1lt0 bb rw fb dcc13dr0 3c # 7c rdi1lt1 bc rw idacr_d fc rw dcc13dr1 3d w 7d rdi1ro0 bd rw idacl_d fd rw dcc13dr2 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 13 of 36 table 6. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw cmp0cr1 50 rw 90 gdi_o_in d0 rw prt4dm1 11 rw cmp0cr2 51 rw 91 gdi_e_in d1 rw prt4ic0 12 rw 52 92 gdi_o_ou d2 rw prt4ic1 13 rw vdac50cr0 53 rw 93 gdi_e_ou d3 rw 14 cmp1cr1 54 rw 94 d4 15 cmp1cr2 55 rw 95 d5 16 56 96 d6 17 vdac51cr0 57 rw 97 d7 18 cscmpcr0 58 # 98 mux_cr0 d8 rw 19 cscmpgoen 59 rw 99 mux_cr1 d9 rw 1a cslutcr0 5a rw 9a mux_cr2 da rw 1b cmpcolmux 5b rw 9b mux_cr3 db rw 1c cmppwmcr 5c rw 9c dac_cr1# dc rw 1d cmpfltcr 5d rw 9d osc_go_en dd rw 1e cmpclk1 5e rw 9e osc_cr4 de rw 1f cmpclk0 5f rw 9f osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 r dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw v2bg_tr e7 rw dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 w dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 w dcc02ou 2a rw amux_cfg1 6a rw sadc_cr2 aa rw bdg_tr ea rw dbc02cr1 2b rw clk_cr3 6b rw sadc_cr3trim ab rw eco_tr eb w dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_ad ad rw ed dcc03ou 2e rw tmp_dr2 6e rw ae ee dbc03cr1 2f rw tmp_dr3 6f rw af ef dbc10fn 30 rw 70 rdi0ri b0 rw f0 dbc10in 31 rw 71 rdi0syn b1 rw f1 dbc10ou 32 rw ace00cr1 72 rw rdi0is b2 rw f2 dbc10cr1 33 rw ace00cr2 73 rw rdi0lt0 b3 rw f3 dbc11fn 34 rw 74 rdi0lt1 b4 rw f4 dbc11in 35 rw 75 rdi0ro0 b5 rw f5 dbc11ou 36 rw ace01cr1 76 rw rdi0ro1 b6 rw f6 dbc11cr1 37 rw ace01cr2 77 rw rdi0dsm b7 rw cpu_f f7 rl dcc12fn 38 rw 78 rdi1ri b8 rw f8 dcc12in 39 rw 79 rdi1syn b9 rw f9 dcc12ou 3a rw 7a rdi1is ba rw fls_pr1 fa rw dbc12cr1 3b rw 7b rdi1lt0 bb rw fb dcc13fn 3c rw 7c rdi1lt1 bc rw fc dcc13in 3d rw 7d rdi1ro0 bd rw dac_cr0# fd rw dcc13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # dbc13cr1 3f rw 7f rdi1dsm bf rw cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 14 of 36 electrical specifications this section presents the dc and ac electr ical specifications for aut omotive cy8c21x45 and cy8c22x45 psoc devices. for the latest electrical specificatio ns, check the most recent data sheet by visiting the web at http://www.cypress.com. specifications are valid for a-grade devices at ?40 c ? t a ? 85 c, t j ? 100 c, and for e-grade devices at ?40 c ? t a ? 125 c, t j ? 150 c, unless noted otherwise. figure 5. voltage vs. cpu frequency for a-grade devices figure 6. voltage vs. cpu frequency for e-grade devices figure 7. imo frequency trim options (a-grade devices only) 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) vdd voltage (v) 0 12 mhz 3.0 v ali d o p er a ti ng re g i o n 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) vdd voltage (v) v a l i d op e r a t i n g r e g i o n 0 12 mhz slimo mode=0 slimo mode=0 slimo mode=1 5.25 4.75 6 mhz 24 mhz imo frequency vdd voltage (v) 0 12 mhz 3.0 3.6 slimo mode=1 [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 15 of 36 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +150 c recommended storage temperature is 25 c 25 c. higher storage temperatures reduce data retention time. t baketemp bake temperature ? 125 see package label ?c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied a-grade devices e-grade devices ?40 ?40 ? ? +85 +125 c c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current in to any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma table 8. operating temperature symbol description min typ max units notes t a ambient temperature a-grade devices e-grade devices ?40 ?40 ? ? +85 +125 c c t j junction temperature a-grade devices e-grade devices ?40 ?40 ? ? +100 +135 c c the temperature rise from ambient to junction is package specific. see table 24 on page 27. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 16 of 36 dc electrical characteristics dc chip level specifications ta b l e 9 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade d evices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. table 9. dc chip level specifications symbol description min typ max units notes v dd supply voltage a-grade devices e-grade devices 3.0 4.75 ? ? 5.25 5.25 v v see table 14 on page 19 i dd supply current a-grade devices, 3.0 v ? v dd ? 3.6 v a-grade devices, 4.75 v ? v dd ? 5.25 v e-grade devices ? ? ? 4 7 8 7 12 15 ma ma ma cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog blocks disabled i sb sleep (mode) current a-grade devices, 3.0 v ? v dd ? 3.6 v a-grade devices, 4.75 v ? v dd ? 5.25 v e-grade devices ? ? ? 3 4 4 12 25 25 ? a ? a ? a everything disabled except ilo, por, lvd, sleep timer, and wdt circuits i sbxtl sleep (mode) current with eco a-grade devices, 3.0 v ? v dd ? 3.6 v a-grade devices, 4.75 v ? v dd ? 5.25 v e-grade devices ? ? ? 4 5 5 13 26 26 ? a ? a ? a everything disabled except eco, por, lvd, sleep timer, and wdt circuits v ref reference voltage (bandgap) 1.275 1.30 1.325 v trimmed for appropriate v dd setting. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 17 of 36 dc general purpose i/o specifications ta b l e 1 0 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade d evices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. dc operational amplifier specifications the following table lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-gr ade devices for the voltage and te mperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unle ss otherwise noted, all specific ations in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3 .3 v at 25c, unless specified otherwise, and are for design guidance only. table 10. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (80 ma maximum combined i oh budget) v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (100 ma maximum combined i ol budget) i oh high-level source current 10 ? ? ma v oh ? v dd ? 1.0 v, see the limitations of the total current in the note for v oh . i ol low-level sink current 25 ? ? ma v ol ? 0.75 v, see the limitations of the total current in the note for v ol . v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 c table 11. dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv i soa supply current (absolute value) a-grade devices e-grade devices ? ? ? ? 30 35 ? a a tcv osoa average input offset voltage drift ? 10 ? ? v/c i eboa [7] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 ? a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0.5 ? v dd ? 1 v note 7. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1 ? 7 for the lowest leakage of 200 na. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 18 of 36 dc sar10 adc specifications ta b l e 1 2 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. dc analog mux bus specifications ta b l e 1 3 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. table 12. dc sar10 adc specifications symbol description min typ max units notes v adcref reference voltage at pin p2[5] when configured as adc reference voltage 3.0 ? 5.25 v when v ref is buffered inside adc, the voltage level at p2[5] (when configured as adc reference voltage) must be always maintained to be at least 300 mv less than the chip supply voltage level on v dd pin. (v adcref < v dd ) i adcref current into p2[5] when configured as adc v ref ? ? 100 a disables the internal voltage reference buffer inl adc integral nonlinearity a-grade devices e-grade devices ?3.0 ?5.0 ? ? 3.0 5.0 lsbit lsbit 10-bit resolution dnl adc differential nonlinearity a-grade devices e-grade devices ?1.5 ?4.0 ? ? 1.5 4.0 lsbit lsbit 10-bit resolution table 13. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 ? r gnd resistance of initializa tion switch to gnd ? ? 800 ? [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 19 of 36 dc por and lvd specifications ta b l e 1 4 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. table 14. dc por and lvd specifications symbol description min typ max units notes v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 01b porlev[1:0] = 10b ? ? 2.82 4.55 2.95 4.73 v v v dd must be greater than or equal to 3.0 v during startup, reset from the xres pin, or reset from watchdog. v ppor1 is only applicable to a-grade devices. v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.95 3.06 4.37 4.50 4.62 4.71 3.02 3.13 4.48 4.64 4.73 4.81 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 20 of 36 dc programming specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. table 15. dc programming specifications symbol description min typ max units notes v ddiwrite supply voltage for flash write operations 3.0 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [8, 9] a-grade devices e-grade devices 1,000 100 ? ? ? ? ? ? erase/write cycles per block flash ent flash endurance (total) [9, 10] cy8c21x45 a-grade devices cy8c22x45 a-grade devices cy8c21x45 e-grade devices cy8c22x45 e-grade devices 128,000 256,000 12,800 25,600 ? ? ? ? ? ? ? ? ? ? ? ? erase/write cycles flash dr flash data retention [9] a-grade devices e-grade devices 10 10 ? ? ? ? years years notes 8. the erase/write cycle limit per block (flash enpb ) is only guaranteed if the device operates within one voltage range. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 9. for the full temperature range, the user must employ a temper ature sensor user module (flashtemp) or other temperature sensor and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. 10. the maximum total number of allowed erase/write cycles is the minimum flash enpb value multiplied by the number of flash blocks in the device. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 21 of 36 ac electrical characteristics ac chip level specifications the following tables list the guaranteed maximum and minimum spec ifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-gr ade devices for the voltage and te mperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unle ss otherwise noted, all specific ations in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3 .3 v at 25 c, unless specified otherwise, and are for design guidance only. figure 8. 24 mhz period jitter (imo) timing diagram table 16. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz a-grade devices, 4.75 v ? v dd ? 5.25 v a-grade devices, 3.0 v ? v dd ? 3.6 v e-grade devices 22.8 22.5 22.3 24 24 24 25.2 [11] 25.5 [11] 25.7 [11] mhz mhz mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 7 on page 14. f imo6 internal main oscillator frequency for 6 mhz a-grade devices e-grade devices 5.5 5.5 6 6 6.5 [11] 6.5 [11] mhz mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 7 on page 14. f cpu1 cpu frequency (5 v v dd operation) a-grade devices e-grade devices 0.089 0.089 ? ? 25.2 [11] 12.6 [11] mhz mhz f cpu2 cpu frequency (3.3 v v dd operation) 0.089 ? 12.6 [11] mhz a-grade devices only f blk5 digital psoc block frequency 0 (5 v v dd operation) a-grade devices e-grade devices 0 0 48 24 50.4 [11, 12] 25.2 [11, 12] mhz mhz refer to table 19 on page 23. f blk33 digital psoc block frequency (3.3 v v dd operation) 0 24 24.6 [11] mhz a-grade devices only f 32k1 ilo frequency 15 32 75 khz this specification applies when the ilo has been trimmed. f 32ku ilo untrimmed frequency 5 ? ? khz after a reset and before the m8c processor starts to execute, the ilo is not trimmed. jitter32k 32 khz rms period jitter ? 100 ? ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % fout48m 48 mhz output frequency 45.6 48.0 50.4 [11] mhz jitter24m1 24 mhz period jitter (imo) ? 300 600 ps f max maximum frequency of signal on row input or row output ? ? 12.6 mhz sr powerup power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time between end of por state and cpu code execution ? 16 100 ms power-up from 0 v. notes 11. accuracy derived from imo with appropriate trim for v dd range 12. refer to the individual user module data sheets for information on maximum frequencies for user modules. jitter24m1 f 24m [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 22 of 36 figure 9. 32 khz period jitter (ilo) timing diagram ac general purpose i/o specifications ta b l e 1 7 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. figure 10. gpio timing diagram ac operational amplifier specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. jitter32k f 32k1 table 17. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.6 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf a-grade devices e-grade devices 3 3 ? ? 18 24 ns ns refer to figure 10 tfallf fall time, normal strong mode, cload = 50 pf a-grade devices e-grade devices 2 2 ? ? 18 28 ns ns refer to figure 10 trises rise time, slow strong mode, cload = 50 pf a-grade devices e-grade devices 7 7 27 32 ? ? ns ns refer to figure 10 tfalls fall time, slow strong mode, cload = 50 pf a-grade devices e-grade devices 7 7 22 28 ? ? ns ns refer to figure 10 tfallf tfalls trisef trises 90% 10% gpio pin output voltage table 18. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv ? ? 100 ns [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 23 of 36 ac digital block specifications the following tables list the guaranteed maximum and minimum spec ifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-gr ade devices for the voltage and te mperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unle ss otherwise noted, all specific ations in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3 .3 v at 25 c, unless specified otherwise, and are for design guidance only. table 19. ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency ( ? 4.75 v) ? ? 50.4 mhz note [14] maximum block clocking frequency (< 4.75 v) ? ? 25.2 mhz v dd < 4.75 v and/or temperature > 85 c timer capture pulse width 50 [13] ? ? ns maximum frequency, no capture ? ? 50.4 mhz note [14] maximum frequency, with or without capture ? ? 25.2 mhz counter enable pulse width 50 [13] ? ? ns maximum frequency, no enable input ? ? 50.4 mhz note [14] maximum frequency, enable input ? ? 25.2 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [13] ? ? ns disable mode 50 [13] ? ? ns maximum frequency ? ? 50.4 mhz note [14] crcprs (prs mode) maximum input clock frequency ? ? 50.4 mhz note [14] crcprs (crc mode) maximum input clock frequency ? ? 25.2 mhz spim maximum input clock frequency ? ? 8.4 mhz maximum nominal data rate is 4 mbps due to 2 x overclocking spis maximum input clock frequency ? ? 4.2 mhz width of ss_ negated between transmissions 50 [13] ? ? ns transmitter maximum input clock frequency maximum input clock frequency with v dd ?? 4.75 v, 2 stop bits ? ? ? ? 25.2 50.4 mhz mhz maximum nominal baud rate is 3 mbaud due to 8 overclocking maximum nominal baud rate is 6 mbaud due to 8 overclocking receiver maximum input clock frequency maximum input clock frequency with v dd ?? 4.75 v, 2 stop bits ? ? ? ? 25.2 50.4 mhz mhz maximum nominal baud rate is 3 mbaud due to 8 overclocking maximum nominal baud rate is 6 mbaud due to 8 overclocking notes 13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). 14. 4.75 v ? v dd ? 5.25 v at ?40 c to 85 c [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 24 of 36 ac external clock specifications the following tables list the guaranteed maximum and minimum spec ifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-gr ade devices for the voltage and te mperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unle ss otherwise noted, all specific ations in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3 .3 v at 25 c, unless specified otherwise, and are for design guidance only. ac sar10 adc specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. ac programming specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. table 20. ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.0 ? 5300 ns ? low period 20.0 ? ?ns ? power-up imo to switch 150 ? ? ? s table 21. ac sar10 adc specifications symbol description min typ max units notes f inadc sar adc input clock frequency ? ? 2 mhz the sample rate of the sar10 adc is equal to f inadc divided by 13. table 22. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz f sclk3 frequency of sclk 0 ? 6 mhz v dd ? 3.6 v t eraseb flash erase time (block) ? 10 40 [15] ms t write flash block write time ? 40 160 [15] ms t dsclk data out delay from falling edge of sclk ? ? 55 ns v dd > 3.6 v, 30 pf load t dsclk3 data out delay from falling edge of sclk ? ? 65 ns 3.0 v ? ? v dd ?? 3.6 v, 30 pf load t prgh total flash block program time (t eraseb + t write ), hot ? ? 100 [15] ms t j ? 0 c t prgc total flash block program time (t eraseb + t write ), cold ? ? 200 [15] ms t j ?? 0 c note 15. for the full temperature range, the user must employ a temperat ure sensor user module (flashte mp) or other temperature senso r and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 25 of 36 ac i 2 c specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications for automotive a-grade and e-grade devices. unless otherwise noted, all specifications in the table apply to a-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 85 c, or 3.0 v to 3.6 v and ?40 c to 85 c. unless otherwise noted, all specifications in the table also apply to e-grade devices for the voltage and temperature ranges of: 4.75 v to 5.25 v and ?40 c to 125 c. typical parameters apply to 5 v and 3.3 v at 25 c, unless specified otherwise, and are for design guidance only. figure 11. definition for timing for fast/standard mode on the i 2 c bus table 23. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 [16] 0 400 [16] khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0 . 6 ? ? s t lowi2c low period of the scl clock 4.7 ?1 . 3 ? ? s t highi2c high period of the scl clock 4.0 ?0 . 6 ? ? s t sustai2c setup time for a repeated start condition 4.7 ?0 . 6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ?100 [17] ?ns t sustoi2c setup time for stop condition 4.0 ?0 . 6 ? ? s t bufi2c bus-free time between a stop and start condition 4.7 ?1 . 3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter ? ?05 0n s notes 16. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is oper ating at 24 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adjusts accordingly. 17. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudati2c ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 26 of 36 packaging information this section provides the packaging specifications for the au tomotive cy8c21x45 and cy8c22x45 psoc devices. the thermal impedances for each package and the typical package capacitance on crystal pins are given. package dimensions figure 12. 28-pin (210-mil) ssop 51-85079 *d [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 27 of 36 figure 13. 48-pin (300-mil) ssop thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 51-85061 *d table 24. thermal impedances per package package typical t ja [18] 28-pin ssop 97.6 c/w 48-pin ssop 69 c/w table 25. typical package capacitance on crystal pins package package capacitance 28-pin ssop 2.8 pf 48-pin ssop 3.3 pf table 26. solder reflow peak temperature package minimum peak temperature [19] maximum peak temperature 28-pin ssop 240 c 260 c 48-pin ssop 240 c 260 c notes 18. t j = t a + power x t ja 19. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 28 of 36 tape and reel information figure 14. 28-pin ssop carrier tape drawing 51-51100 *b [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 29 of 36 figure 15. 48-pin ssop carrier tape drawing 51-51104 *d table 27. tape and reel specifications package cover tape width (mm) hub size (inches) minimum leading empty pockets minimum trailing empty pockets standard full reel quantity 28-pin ssop 13.3 7 42 25 1000 48-pin ssop 25.5 4 32 19 1000 [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 30 of 36 development tool selection this section presents the development tools available for the automotive cy8c21x45 and cy8c22x45 families. software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for years. psoc designer is available free of charge at http://www.cypress.com. psoc designer comes with a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purchased from the cypress online store. the online store also has the most up to date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. advanced emulation features are also supported through psoc designer. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi 28-pin cy8c29466-24pxi pdip psoc device samples (two) psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12 v) european plug adapter usb 2.0 cable getting started guide development kit registration form cy3280-22x45 universal capsense controller board the cy3280-22x45 controller board is an additional controller board for the cy3280-bk1 universal capsense controller kit . the universal capsense controller kit is designed for easy prototyping and debug of capsense designs with pre-defined control circuitry and plug-in hardware. the cy3280-22x45 kit contains no plug-in hardware. t herefore, it is only usable if plug-in hardware is purchased as part of the cy3280-bk1 kit or other separate kits. the kit includes: cy3280-22x45 universal capsense controller board cy3280-22x45 universal capsense controller board cd dc power supply printed documentation cy3280-cpm1 capsenseplus module the cy3280-cpm1 capsenseplus module is a plug-in module board for the cy3280-22x45 capsense controller board kit. this plug-in module has no capacitive sensors on it. instead, it has other general circuitry (such as a seven-segment display, potentiometer, leds, buttons, thermistor) that can be used to develop applications that require capacitive sensing along with other additional functionality. to use this kit, a cy3280-22x45 kit is required. evaluation tools all evaluation tools can be purc hased from the cypress online store. the online store also has the most up-to -date information on kit contents, descripti ons, and availability. cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, an rs-232 port, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (two) psoc designer software cd getting started guide usb 2.0 cable [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 31 of 36 device programmers all device programmers can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows the user to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. this software is free and can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240-v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 28. emulation and programming accessories part number pin package pod kit [20] foot kit [21] prototyping module adapter [22] cy8c21345-24pvxa cy8c21345-12pvxe cy8c22345-24pvxa cy8c22345h-24pvxa CY8C22345-12PVXE 28-pin ssop cy3250-22345 cy3250-28sso p-fk ? as-28-28-02ss-6enp-gang cy8c21645-24pvxa cy8c21645-12pvxe cy8c22645-24pvxa cy8c22645-12pvxe 48-pin ssop ? ? ? as-48-48-01ss-6-gang notes 20. pod kit contains an emulation pod, a flex-cable (co nnects the pod to the ice), two feet, and device samples. 21. foot kit includes surface mount feet that can be soldered to the target pcb. 22. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 32 of 36 ordering information the following table lists the key package features and ordering codes of the automotive cy8c21x45 and cy8c22x45 device families . table 29. psoc device family key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 28-pin (210-mil) ssop cy8c21345-24pvxa 8 k 512 ?40 c to +85 c 4 6 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c21345-24pvxat 8 k 512 ?40 c to +85 c 4 6 24 24 0 yes 28-pin (210-mil) ssop cy8c21345-12pvxe 8 k 512 ?40 c to +125 c 4 6 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c21345-12pvxet 8 k 512 ?40 c to +125 c 4 6 24 24 0 yes 28-pin (210-mil) ssop cy8c22345-24pvxa 16 k 1 k ?40 c to +85 c 8 6 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c22345-24pvxat 16 k 1 k ?40 c to +85 c 8 6 24 24 0 yes 28-pin (210-mil) ssop cy8c22345h-24pvxa 16 k 1 k ?40 c to +85 c 8 6 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c22345h-24pvxat 16 k 1 k ?40 c to +85 c 8 6 24 24 0 yes 28-pin (210-mil) ssop CY8C22345-12PVXE 16 k 1 k ?40 c to +125 c 8 6 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) CY8C22345-12PVXEt 16 k 1 k ?40 c to +125 c 8 6 24 24 0 yes 48-pin (300-mil) ssop cy8c21645-24pvxa 8 k 512 ?40 c to +85 c 4 6 38 38 0 yes 48-pin (300-mil) ssop (tape and reel) cy8c21645-24pvxat 8 k 512 ?40 c to +85 c 4 6 38 38 0 yes 48-pin (300-mil) ssop cy8c21645-12pvxe 8 k 512 ?40 c to +125 c 4 6 38 38 0 yes 48-pin (300-mil) ssop (tape and reel) cy8c21645-12pvxet 8 k 512 ?40 c to +125 c 4 6 38 38 0 yes 48-pin (300-mil) ssop cy8c22645-24pvxa 16 k 1 k ?40 c to +85 c 8 6 38 38 0 yes 48-pin (300-mil) ssop (tape and reel) cy8c22645-24pvxat 16 k 1 k ?40 c to +85 c 8 6 38 38 0 yes 48-pin (300-mil) ssop cy8c22645-12pvxe 16 k 1 k ?40 c to +125 c 8 6 38 38 0 yes 48-pin (300-mil) ssop (tape and reel) cy8c22645-12pvxet 16 k 1 k ?40 c to +125 c 8 6 38 38 0 yes [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 33 of 36 ordering code definitions cy 8 c 2x xxx x-spxx package type: thermal rating: px = pdip pb-free a = automotive ?40 c to +85 c sx = soic pb-free c = commercial pvx = ssop pb-free e = automotive extended ?40 c to +125 c lfx/ltx = qfn pb-free i = industrial ax = tqfp pb-free cpu speed: 12/24 mhz optional part number modifier: h = integrated immersion ? touchsense ? technology part number family code (21, 22) technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress semiconductor [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 34 of 36 document conventions acronyms used units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?0x?, or ?b? are decimal. table 30. acronyms acronym description ac alternating current adc analog-to-digital converter aec automotive electronics council api application programming interface cpu central processing unit crc cyclic redundancy check ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory erm eccentric rotating motor fsr full scale range gpio general purpose i/o ice in-circuit emulator ide integrated development environment i/o input/output ilo internal low-speed oscillator imo internal main oscillator ipor imprecise power on reset lsbit least significant bit lvd low voltage detect msbit most significant bit pc program counter pcb printed circuit board por power on reset ppor precision power on reset prs pseudo-random sequence psoc programmable system-on-chip pwm pulse width modulator ram random access memory rom read only memory sc switched capacitor smp switch mode pump spi serial peripheral interface uart universal asynchronous receiver/transmitter table 31. units of measure symbol unit of measure c degree celsius db decibels ff femto farad hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k ? kilohm lsbit least significant bit mbaud megabaud mbps megabits per second mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? v microvolts ? vrms microvolts root-mean-square ? w microwatts ma milliampere ms millisecond mv millivolts na nanoampere ns nanosecond nv nanovolts ? ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second ? sigma: one standard deviation v volts [+] feedback
cy8c21345, cy8c21645 cy8c22345, cy8c22 345h, cy8c22645 document number: 001-55397 rev. *i page 35 of 36 document history page document title: cy8c21345, cy8c21645, cy8c22345, cy8c22345h, cy8c22645 automotive psoc ? programmable system-on-chip? document number: 001-55397 revision ecn orig. of change submission date description of change ** 2759868 vivg 09/04/09 new datasheet *a 2788690 vivg 10/20/09 added 48 ssop to the marketing part numbers. corrected the i soa spec in table 13/14. changed the thetaja values based on pe inputs. *b 2792800 vivg 10/26/09 corrected typo in ordering in formation table (digital i/o for 48-ssop devices) *c 2822630 btk 12/07/09 added cy8c22345h device s and updated features section and psoc functional overview section to include haptics device information. updated features section. added contents sect ion. updated psoc functional overview section. updated block diagram of device. updated psoc device character- istics table. updated pinouts section. fix ed issues with the register map tables. added a figure for slimo configurat ion. updated footnotes for the dc programming specifications table. corrected v ddiwrite and flash ent electrical specifications. updated ordering informati on section. added development tool selection section. combined 5 v dc operational amplifier specifications table with 3.3 v dc operational amplifier specif ications table. updated all ac speci- fications to conform to 5% imo accu racy and 8.33% slimo accuracy. split up electrical specifications for a-grade and e-grade devices in the absolute maximum ratings, operating temperatur e, dc chip level specifications, dc programming specifications, and ac chip -level specifications tables. added solder reflow peak temperature table. added t prgh , t prgc , i ol , i oh , f 32ku , dc ilo , and t powerup electrical specifications. added maximum values and updated typical values for t eraseb and t write electrical specifications. replaced t ramp electrical specification with sr powerup electrical specification. this revision fixes cdt 62018. *d 2905459 njf 04/06/10 updated cypress website links added t baketemp , t baketime , and fout48m electrical specifications removed sections ?third party tools? ?build a psoc emulator into your board? updated package diagrams updated ordering information table updated solder reflow peak temperature specifications. updated the getting started and desi gning with psoc designer sections. converted data sheet from preliminary to final fixes from cdt 72358: deleted 5% oscillator accuracy reference in the features section. deleted reference to a specific sar10 adc sample rate in the analog system section. updated the follo wing electrical specifications: i dd , i sb , i sbxtl , v ref , v cmoa , i adcref , inl adc , dnl adc , v ppor2 , flash dr , f imo24 , trisef, tfallf, trises, tfalls. deleted the sps adc electrical specification, the dc low power comparator specific ations, the ac low power comparator specifica- tions, and the ac analog mux bus specifications. *e 2915673 vivg 04/16/10 post to external web *f 2991841 btk 07/23/10 added a cl arifying note to the v ppor1 electrical specification. added CY8C22345-12PVXE(t) devices. moved document conventions to the end of the document. this revision fixes the following cdts: 72476, 75127, 78329. *g 3037161 btk 09/23/10 adde d cy8c21345-12pvxe(t) devices to the ordering info rmation section. *h 3085024 btk 11/12/10 added cy8c21 645-12pvxe(t), cy8c21645-24pvxa(t), cy8c22645-12pvxe(t), and cy8c22645-24pvxa(t) devices to the ordering information section. refer to cdt 87793. *i 3200275 btk 03/18/11 added tape and reel packaging information (cdt 96026). [+] feedback
document number: 001-55397 rev. *i revised march 18, 2011 page 36 of 36 psoc designer? is a trademark and psoc? is a registered trademark of cypress semiconductor corp. all other trademarks or regist ered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associated comp anies conveys a license under th e philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. all products and company nam es mentioned in this document may be the trademarks of their respective holders. cy8c21345, cy8c21645 cy8c22345, cy8c22345h, cy8c22645 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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